1. Field of the Invention
The present invention relates to a semiconductor technology, and particularly to a semiconductor device and a fabrication method thereof.
2. Description of the Prior Art
In general, there are two basic types of non-volatile memory (NVM) cell structures: stack-gate and split-gate. The stack-gate memory cell usually has a floating gate and a control gate, with the control gate being positioned directly above the floating gate. Recently, MONOS or SONOS structure is also developed to replace floating gate with ONO. In a split-gate structure the control gate is still positioned above the floating gate, but it is offset laterally from it. Another split-gate structure includes for example a select gate formed overlying a portion of a channel region adjacent the source region. The select gate is electrically isolated from a control gate formed overlying a portion of a channel region adjacent the drain region. The select gate controls channel current.
Conventionally, the select gate is formed in a way similar to forming a spacers utilizing an anisotropic etch process, and a width of 1.5 T of a split gate structure can be obtained. As shown in FIG. 1, after a gate structure 12 is formed on a semiconductor substrate 10, a selective gate material layer 14 is deposited. Thereafter, as shown in FIG. 2, undesired portion of the selective gate material layer 14 is removed by etching through a photoresist layer 16. Thereafter, as shown in FIG. 3, an anisotropic etch process is performed to remove the photoresist layer 16, if any left in the previous etch process, and to forma select gate 18 in a spacer shape. Accordingly, the obtained split gate structure can have a width of the width of 1.5 transistors, denoted as 1.5 T. However, because the shape of the select gate relies on the anisotropic properties of the etch process, it is difficult to control the shape finally obtained. Furthermore, as the procedures are similar to those for forming spacers, the upper portion of the obtained select gate always has a width (line width) gradually decreasing toward the top, and it is difficult to increase the width along the upper portion.
In the demands for minimizing the memory device size and fabrication cost, the size of the split gate structure having a select gate is also wanted to be minimized. However, even though the width of the control gate can be decreased in accordance with the minimization of the feature size benefit from an improved process limit in the future, the select gate width may be still limited to an acceptable scale, such that the split gate structure may be unable to meet the desired width of 1.5 T. The reason is if the width of the select gate having a spacer shape is further minimized, the width of the upper portion will be too narrow to maintain its properties or performance. Accordingly, there is still a need for a novel method of forming a split gate structure having a select gate with good performance to meet a demand of a minimized size.